1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device comprising a gate electrode.
2. Description of the Related Art
There are two types of semiconductor memory devices. The first type is known as a RAM and the second type is known as a ROM. The RAM devices, such as a DRAM and an SRAM, are volatile (i.e., data is erased when power to the memory cell is turned off) and data is quickly inputted and outputted. The ROM is non-volatile and data is more slowly inputted and outputted. Among the ROM devices, demand is great for EEPROM (electrically erasable and programmable ROM) or a flash memory in which data is electrically inputted and outputted.
A fundamental structure in a semiconductor device is a transistor, which generally include a gate electrode. The gate electrode that is included in a respective cell of the semiconductor device is required to have a fine line width and a low resistance. Furthermore, the gate electrode needs to have a constant resistance value for all memory cell transistors across a wafer in order to improve reliability of inputting and outputting of data to and from the respective cell.
FIGS. 1A to 1E illustrate sectional views of stages in a conventional method of manufacturing a non-volatile memory device.
Referring to FIG. 1A, a gate oxide film (not shown) is formed on a semiconductor substrate 10 having a field area and an active area divided by a conventional isolation process. A conductive layer is formed on the gate oxide film in order to form a floating gate. After forming a dielectric film on the conductive layer, a polysilicon layer is formed on the dielectric film, which is used for a control gate. An insulating material, such as a nitride, is deposited to a thickness of 800-1500 xc3x85 on the polysilicon layer to form a hard mask layer.
The hard mask layer is patterned via a photolithography process to form a hard mask pattern 18 for patterning the gate electrode. The polysilicon layer, the dielectric film and the conductive layer are then continuously and anisotropically etched using the hard mask pattern 18 as an etching mask, thereby forming a gate structure 20 in which a gate oxide film pattern (not shown), the conductive pattern 12, the dielectric pattern 14 and the polysilicon pattern 16 and the hard mask pattern 18 are stacked.
When the anisotropic etching is performed in order to form the gate structure 20, the hard mask pattern 18 used as the etching mask also is partially etched due to the impact of an ion beam. However, the hard mask pattern 18 on the polysilicon layer pattern 16 is not etched to a uniform thickness throughout a whole pattern as a result of the etching. Accordingly, the hard mask pattern 18 has a non-uniform thickness within one gate structure 20 and also among various gate structures across a wafer.
Referring to FIG. 1B, an insulating material, such as an oxide, is deposited on the resultant structure shown in FIG. 1A. Then, the insulating material is anisotropically etched to form a gate spacer 22. A stopping layer 24 having a thickness of 500-800 xc3x85 is continuously formed on the gate spacer 22, the semiconductor substrate 10 and the gate structure 20. The stopping layer 24 includes an insulating material, such as a nitride. The stopping layer 24 indicates a stopping point when performing a subsequent polishing process for an insulating interlayer and is also used to self-align the contacts when forming contacts between the gate electrodes in a subsequent process.
Referring to FIG. 1C, as described above, a nitride film 26, which includes the hard mask pattern 18 and the stopping layer 24, is deposited on the respective polysilicon layer pattern 16. Even though the stopping layer 24 is uniformly deposited, the nitride film 26 which includes the hard mask pattern and the stopping layer may not have a uniform thickness because of a non-uniform thickness of the hard mask pattern 18 remaining on the respective polysilicon layer pattern 16.
As shown in FIGS. 1C and 1D, an insulating interlayer 28 is then formed to cover the resultant structure shown in FIG. 1B, which includes the stopping layer 24. Then, a planarization process is performed to expose the polysilicon layer pattern 16.
Referring firstly to FIG. 1C, the insulating interlayer 28 is formed in order to cover the resultant structure, including the stopping layer 24. Then, the insulating interlayer 28 is chemically and mechanically polished to expose the stopping layer 24, as shown in FIG. 1C. In order to perform the polishing process for exposing the stopping layer 24, a polishing rate of the nitride film should be slower than the polishing rate of the insulating interlayer oxide film 28.
As described above, since the nitride film 26, which is a top layer of the respective gate structure, has a non-uniform thickness, the nitride film 26 remaining on the polysilicon layer pattern 16 also has a non-uniform thickness after the chemical and mechanical polishing.
Referring now to FIG. 1D, the stopping layer 24 covering the hard mask pattern and the hard mask pattern 18 are removed to expose the polysilicon layer pattern 16. That is, the nitride film 26 formed on the polysilicon layer pattern 16 is removed. The removal of the nitride film 26 is carried out via a dry etching or a wet etching process.
Since the nitride film 26 formed on the respective polysilicon layer pattern 16 has a non-uniform thickness, the polysilicon layer pattern 16 also has a non-uniform thickness. Similarly, an exposed portion of the polysilicon layer pattern 16 has a different area at different locations across the wafer 10 when the nitride film 26 is removed.
Particularly, when the dry etching is performed to remove the nitride film 26, the polysilicon layer pattern 16 is continuously and gradually etched at a portion in which the nitride film 26 remaining on the polysilicon layer pattern 16 is thin so that the thickness of the polysilicon layer pattern 16 is reduced at that portion by the time the nitride film 26 is completely etched on the entire polysilicon layer pattern 16. Furthermore, the gate spacer 22 is also etched thereby exposing a sidewall of the polysilicon layer pattern 16. Therefore, after the nitride film 26 is completely etched, the thickness of the polysilicon layer pattern 16 is thinner at the portion where the thickness of the nitride film 26 on the polysilicon layer pattern 16 was thinner before the etching rather than at a portion where the thickness of the nitride film 26 was thicker before the etching.
If the nitride film 26 is removed by a wet etching, an etchant penetrates into the sidewall of the gate spacer 22 so that a portion of the stopping layer 24 formed on the sidewall of the gate spacer 22 is removed. At that time, the portion of the stopping layer 24a formed on the sidewall of the gate spacer 22 is removed non-uniformly due to the non-uniformity in the thickness of the nitride film 26. Accordingly, the sidewall of the respective polysilicon layer pattern has a different exposed area.
Referring to FIG. 1E, a metal silicide layer 30 is selectively deposited on the exposed polysilicon layer pattern 16 to form a gate electrode. However, an area where the metal silicide layer 30 is formed is different at different locations because an area where the polysilicon layer pattern 16 is exposed is different at different locations on the wafer. Further, since the polysilicon layer pattern 16 has non-uniform thickness, the thickness of the gate electrode varies within one gate stack and also at different locations across the wafer.
As described above, in a conventional process of making a non-volatile memory device, since the polysilicon layer pattern for forming the gate electrode is formed non-uniformly, the gate electrodes have varying resistances at different locations across the wafer surface. Accordingly, the reliability of the semiconductor device is reduced.
The present invention is intended to solve the aforementioned non-uniform gate resistance problem, and accordingly it is a first feature of an embodiment of the present invention to provide a method of forming a gate electrode in which a non-uniformity in a resistance thereof is reduced.
It is a second feature of an embodiment of the present invention to provide a method of manufacturing a non-volatile semiconductor device having a gate electrode in which the non-uniformity in the resistance of the gate electrode is reduced.
To provide the first feature of an embodiment of the present invention, a method of forming a gate electrode of a semiconductor device is provided. In the method of forming a gate electrode of a semiconductor device, an oxide film pattern, a polysilicon layer pattern and a hard mask pattern in that order are sequentially stacked on a semiconductor substrate to form a gate structure. A gate spacer is formed on a sidewall of the gate structure, wherein the gate spacer includes an oxide-based insulating material. The hard mask pattern, which is stacked on a top portion of the gate structure, is removed to expose the polysilicon layer pattern. The polysilicon layer pattern and a top portion of the gate spacer are planarized by removing a top portion of the gate spacer that was around the hard mask pattern and projected above the polysilicon layer pattern.
The method of forming a gate electrode of a semiconductor device may further include continuously forming a stopping layer on the polysilicon layer pattern, the gate spacer and the semiconductor substrate; forming an insulating interlayer on the stopping layer; and exposing a surface of the polysilicon layer pattern by planarizing the insulating interlayer. Exposing the surface of the polysilicon layer pattern by planarizing the insulating interlayer may include performing a chemical and mechanical polishing until the surface of the stopping layer is exposed and etching the exposed stopping layer to expose the surface of the polysilicon layer pattern.
The method of forming a gate electrode of a semiconductor device may further include selectively forming a metal silicide layer on the surface of the exposed polysilicon layer after the surface of the polysilicon layer pattern is exposed.
To provide the second feature of an embodiment of the present invention, a method of forming a non-volatile semiconductor device is provided. In the method of forming a non-volatile semiconductor device, an oxide film, a conductive layer, a dielectric layer, a polysilicon layer and a hard mask layer comprised of a nitride film in that order are sequentially formed on a semiconductor substrate. A predetermined portion of the hard mask layer is etched to form a hard mask pattern. The polysilicon layer, the dielectric layer, the conductive layer and the oxide film are sequentially etched using the hard mask pattern as an etching mask to form a gate structure in which an oxide film pattern, a conductive layer pattern, a dielectric layer pattern, a polysilicon layer pattern and a hard mask pattern are stacked on the semiconductor substrate. A gate spacer is formed on a sidewall of the gate structure, wherein the gate spacer includes an oxide-based insulating material. The hard mask pattern, which is stacked on a top portion of the gate structure, is removed to expose the polysilicon layer pattern. The polysilicon layer pattern and a top portion of the gate spacer are planarized by removing a top portion of the gate spacer that was around the hard mask pattern and projected above the exposed polysilicon layer pattern. A continuous stopping layer is then formed on the resulting exposed polysilicon layer pattern, the gate spacer and the semiconductor substrate. After forming an insulating interlayer on the stopping layer, the surface of the polysilicon layer pattern is exposed by planarizing the insulating interlayer.
In the method of forming a non-volatile semiconductor device, exposing a surface of the polysilicon layer pattern by planarizing the insulating interlayer may include performing a chemical and mechanical polishing until a surface of the stopping layer is exposed and etching the exposed stopping layer to expose the surface of the polysilicon layer pattern. The method of forming a non-volatile semiconductor device may further include selectively forming a metal silicide layer on the surface of the exposed polysilicon layer after exposing the surface of the polysilicon layer pattern.
According to the present invention, since subsequent processes are performed after removing the hard mask pattern, the respective film forming the gate electrode has a uniform thickness while being uniformly exposed. Therefore, it is possible to manufacture the semiconductor device having a gate electrode with a reduced difference in a thickness thereof and, consequently, in the gate resistance across the wafer.